1 1 1/12/01 supertex inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." supertex does not assume responsibility for use of devices described and limits its liabi lity to the replacement of devices determined to be defective due to workmanship. no responsibility is assumed for possible omissions or inaccuracies. circuitry and specifications are subject to c hange without notice. for the latest product specifications, refer to the supertex website: http://www.supertex.com. for complete liability information on all supertex products, refer to the most curre nt databook or to the legal/disclaimer page on the supertex website. TN5325 low threshold n-channel enhancement-mode v ertical dmos fets bv dss /r ds(on) v gs(th) i d(on) bv dgs (max) (max) (min) to-236ab* to-92 to-243aa** 250v 7.0 ? 2.0v 1.2a TN5325k1 TN5325n3 TN5325n8 * same as sot-23. all units shipped on 3,000 piece carrier tape reels. ** shipped on 2,000 piece carrier tape and reels. order number / package product marking for sot-23: n3c ? where ? = 2-week alpha date code ordering information absolute maximum ratings drain-to-source voltage bv dss drain-to-gate voltage bv dgs gate-to-source voltage 20v operating and storage temperature -55 c to +150 c soldering temperature* 300 c * distance of 1.6 mm from case for 10 seconds. features ? low threshold ?2.0v max. ? free from secondary breakdown ? low power drive requirement ? low c iss and fast switching speeds ? excellent thermal stability ? high input impedance and high gain ? complementary n- and p-channel devices applications ? logic level interfaces ?ideal for ttl and cmos ? solid state relays ? battery operated systems ? photo voltaic drives ? analog switches ? general purpose line drivers ? t elecom switches advanced dmos technology these enhancement-mode (normally-off) transistors utilize a vertical dmos structure and supertex? well-proven silicon-gate manufacturing process. this combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inher- ent in mos devices. characteristic of all mos structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. supertex? vertical dmos fets are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. note: see package outline section for dimensions. package options s g d t o-92 t o-243aa (sot-89) g d s d t o-236ab (sot-23) g s d product marking for to-243aa where ? = 2-week alpha date code tn3c ?
2 1235 bordeaux drive, sunnyvale, ca 94089 tel: (408) 744-0100 ?fax: (408) 222-4895 www.supertex.com 1 1/12/01 ?001 supertex inc. all rights reserved. unauthorized use or reproduction prohibited. package i d (continuous)* i d (pulsed) power dissipation jc ja i dr *i drm @ t a = 25 c c/w c/w to-236ab 150ma 400ma 0.36w 200 350 150ma 400ma to-92 215ma 800ma 0.74w 125 170 215ma 800ma to-243aa 316ma 1.5a 1.6w** 15 78** 316ma 1.5a * i d (continuous) is limited by max rated t j . **mounted on fr5 board. 25mm x 25mm x 1.57mm. significant p d increase possible on ceramic substrate. thermal characteristics symbol parameter min typ max unit conditions bv dss drain-to-source breakdown voltage 250 v i d = 100 a, v gs = 0v v gs(th) gate threshold voltage 0.6 2.0 v v gs = v ds , i d = 1ma ? v gs(th) change in v gs(th) with temperature -4.5 mv/ ci d = 1ma, v gs = v ds i gss gate body leakage 100 na v gs = 20v, v ds = 0v i dss zero gate voltage drain current 1.0 av gs = 0v, v ds = 100v 10.0 av gs = 0v, v ds = max rating 1.0 ma v gs = 0v, v ds = 0.8 max rating t a = 125 c i d(on) on-state drain current 0.6 a v gs = 4.5v, v ds = 25v 1.2 v gs = 10v, v ds = 25v r ds(on) static drain-to-source 8.0 ? v gs = 4.5v, i d = 150ma on-state resistance 7.0 ? v gs = 10v, i d = 1.0a ? r ds(on) change in r ds(on) with temperature 1.0 %/ cv gs = 4.5v, i d = 150ma g fs forward transconductance 150 m v ds = 25v, i d = 200ma c iss input capacitance 110 c oss common source output capacitance 60 pf v gs = 0v, v ds = 25v, f = 1mhz c rss reverse transfer capacitance 23 t d(on) turn-on delay time 20 t r rise time 15 t d(off) turn-off delay time 25 t f fall time 25 v sd diode forward voltage drop 1.8 v i sd = 200ma, v gs = 0v t rr reverse recovery time 300 ns i sd = 200ma, v gs = 0v notes: 1.all d.c. parameters 100% tested at 25 c unless otherwise stated. (pulse test: 300 s pulse, 2% duty cycle.) 2.all a.c. parameters sample tested. electrical characteristics (@ 25 c unless otherwise specified) v dd = 25v ns i d = 150ma r gen = 25 ? ? switching waveforms and test circuit 90% 10% 90% 90% 10% 10% pulse generator v dd r l output d.u.t. t (on) t d(on) t (off) t d(off) t f t r input input output 10v v dd r gen 0v 0v TN5325
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